This invention relates to integrated circuits and, more particularly to an integrated circuit design approach.
The design of highly complex systems within a single integrated circuit is the new challenge to the integrated circuit design community. Driven by the need for high speed and large throughput applications, it has become quite evident that the design of very large-scale integrated circuits (VLSI) can be undertaken most advantageously only by adopting a policy of reuse at a cores level. Such reuse not only permits the effective design of very complex chips, but also offers such designs in very short time. In such a re-use approach, cores that are available from previous in-house designs, or from other commercial concerns, are interconnected to form a system on a chip (SoC), in a manner not unlike the way integrated circuits are interconnected on printed circuit wiring boards. Cores are available that implement CPUs, memories, network controllers, UARTs, etc. The advantage of using cores lies in the fact that these designs have been perfected in the past (debugged and thoroughly verified) and can be assumed to be operationally correct.
It is noted that some SoC designs require functionalities that are not available by simply interconnecting available cores and, therefore, those designs include one or more specially designed user-defined logic (UDL) modules. A UDL module may contain more than mere combinatorial logic.
In the context of this disclosure, the term “cores” designates pre-packaged design modules that a designer of an integrated circuit employs, usually without any changes. A UDL module represents functional elements of an integrated circuit design that combine with the cores to form the integrated circuit's functional circuitry.
Alas, the use of cores to design an integrated circuit is not sufficient when it comes to verifying a completed integrated circuit design, because the system's global design or an existing UDL might contain errors, interfaces between the cores might not have been accounted for in a proper way in the initial design phase, or the layout might not have been designed properly.
The myriad sources of possible manufacturing defects in SoCs make it imperative that the SoCs should be testable. Often, cores have an associated suite of tests that is available so, if a core within an SoC can be accessed, at least the cores can be tested. That makes the testing of even very highly complex designs feasible, provided that a mechanism is incorporated for accessing each of the embedded cores in an SoC design.
The notion of a wrapper arose to provide precisely this capability. A wrapper comprises circuitry that surrounds a core, and which is accessible (though not necessarily directly) from outside the SoC. It is said that a wrapper “surrounds” a core because all inputs and output of a core are accessible only by going through the wrapper. Put another way, a wrapper has inner I/O leads to which the associated core's I/O leads are connected, and outer I/O leads. Each inner I/O lead has a corresponding outer I/O lead. A wrapper typically has several additional outer I/O leads.
FIG. 1 depicts the structure of a wrapper that comports with the IEEE proposed P1500 standard. See, for example, http://grouper.ieee.org/groups/1500/. It includes a wrapper 10 that wraps, or encompasses, core 20 in the sense defined above. A wrapper serial input 18 is applied to a shift register-like set of wrapper input-interface cells 13, from whence it is applied to a serial register-like set of wrapper output cells 14. The serial output of set 14 is applied to multiplexer 15. The serial input is also applied to multiplexer 15 (a different input lead) through bypass register 17, which typically provides a one-bit delay. Lastly, the serial input is applied to wrapper control element 11 that comprises a wrapper instruction register 11-1 that receives the serial input and applies the information that is stored in instruction register 11-1 to controller 11-2. Actually, register 11-1 is both a serial input/output register and a parallel input/output register. The parallel input to register 11-1 is applied from outside wrapper 10 via bus 12, and the serial output is applied to a first input of multiplexer 16. The output of multiplexer 15 connects to a second input of multiplexer 16, and the output of multiplexer 16 forms the serial output of wrapper 10. Controller 11-2 controls the input cells set, the output cells set, and multiplexers 15 and 16.
An external tester applies test vectors for a core at a set of pins of the SoC. The paths between these pins and the wrapper of the core is referred to as a Test Access Mechanism, or TAM. The TAM is user-defined and it is not part of the P1500 standard.
S. Koranne, in “A Novel Reconfigurable Wrapper for Testing of Embedded Core-Based SOCs and its Associated Scheduling Algorithm,” volume 21 of Journal of Electronic Testing, pages 51–70, Kluwer Academic Publishers, September 2002 addresses the issue of TAM optimization in conjunction with efficient scheduling of tests on system level. Koranne observes that since the number of test pins that are available at ports of the integrated circuit (IC) is limited, test bits ought to be partitioned in order to reduce the total test cost. Observing that previous approaches have designed test wrapper around cores assuming a static width of TAM, Koranne describes an approach the number of TAM bits that are processed in parallel by the wrapper can be changed, rather than being fixed. Koranne terms this a “reconfigurable wrapper design.”
Regardless of what Koranne calls his approach, it remains an approach that offers control only over the number of TAM bits that are employed in the testing of a core within an SoC. At best, it can be said that such control is control over a parameter of the TAM. The functionality of the wrapper is unaltered by anything that Koranne suggests.
However, the complexity of SoC designs makes it highly advantageous to adopt an architecture, and a design paradigm, that employs an approach that exercises control over the functionality of the wrapper and, consequently, is able to affect the functionality of the core+wrapper combination.